Frequency synthesizer systems and methods are widely used in radio communications to produce accurate discrete frequency steps. Frequency synthesizer systems and methods generally include a phase locked loop (PLL).
FIG. 1 illustrates a conventional digital frequency synthesizer including a phase locked loop. As shown in FIG. 1, the phase locked loop 100 includes a controlled oscillator, such as a voltage controlled oscillator (VCO) 110 that is responsive to a frequency control input signal 112, to generate an output frequency 114. The output frequency 114 is applied to a programmable frequency divider 120 that is responsive to a divider control input 122 to divide the output frequency 114, and thereby produce a divided signal 124. A phase detector 130, also referred to as a phase comparator, compares the divided signal 124 and a reference frequency signal 132 to produce an error signal 134 if the frequency or phase is not the same. Reference frequency signal 132 may be produced by a stable frequency source, such as a crystal oscillator, and may be divided down using a reference divider.
The error signal 134 is filtered in loop filter 140. Thus, loop filter 140 filters the error signal 134 to produce the frequency control input 112 to the controlled oscillator. By controlling the programmable frequency divider 120 to divide by different N-values, for example using N control bits as a divider control input 122, the output frequency 114 that is generated by the controlled oscillator 110 can be controlled to any integer multiple of the reference frequency signal 132, i.e. in discrete steps of the reference frequency.
In many frequency synthesizer applications, it is desirable to tune to new output frequencies rapidly. Unfortunately, the loop filter may preclude rapid tuning. Accordingly, it is known to alter the characteristics of the loop filter during tuning to increase its bandwidth.
FIG. 2 illustrates a first embodiment of a conventional loop filter 140'. As shown, loop filter 140' includes an integrator 202 comprising a serially connected resistor R and capacitor C.sub.1. A second capacitor C.sub.2 is also provided in parallel with the integrator 202. In order to increase tuning speed of the phase locked loop, it is known to provide a primary charge pump 204 for the loop filter 140. The primary charge pump 204 is directly or indirectly responsive to the error signal 134, to speed the transfer of charge to the loop filter capacitors. The charge pump produces a pump current I.sub.p which is used to charge or discharge capacitors C.sub.1 and C.sub.2.
For loop stability reasons, C.sub.1 is generally much larger than C.sub.2 in value. Therefore, the length of time it takes to transfer charge to C.sub.1 generally dominates the time it takes for the phase locked loop to lock onto a new frequency. Accordingly, it is known to increase the loop bandwidth by increasing the output current I.sub.p of the primary charge pump 204. Since increasing the charge pump current generally also decreases the damping factor, it is known to switch an additional resistor into the loop filter to maintain the damping factor constant. Accordingly, as shown in FIG. 3, it is known to provide a loop filter 140" which includes an additional resistor R.sub.s and a switch such as a field effect transistor 302, to switch the additional resistor R.sub.s into the loop filter 140" and maintain the damping factor constant. This additional resistor and switch known as a Fastlock Circuit Implementation, is used in frequency synthesizers marketed by National Semiconductor, as described in "National Semiconductor Products for Wireless Communications Databook", 1997, p. 1-98.
It is also known to provide an integral charge pump in addition to the primary charge pump. Accordingly, as shown in FIG. 4, loop filter 140'" includes an integral charge pump 402 in addition to the primary charge pump 204. Both the integral charge pump 402 and the primary charge pump 204 are responsive, directly or indirectly, to the error signal 134 from phase detector 130 of FIG. 1. As shown, integral charge pump 402 is connected so that it can charge or discharge capacitor C.sub.1 directly. Thus, an integral charge pump current I.sub.i can be applied to capacitor C.sub.1 without the charge pump being limited by the voltage supply rail. The integral charge pump 402 is then switched off by the error signal 134 after a short time, to allow the phase locked loop to settle on the desired frequency.
Unfortunately, it make take an excessively long time for the phase locked loop to lock onto a new frequency using any of the loop filters of FIGS. 2-4. In particular, it will generally require multiple reference cycles to lock using these loop filters. For example, for fast locking loops which are used in cellular telephony applications, such as for GSM telephones, the number of cycles may be on the order of 160. This may place a limit on how fast a phase locked loop can change frequencies.
A specific example of a frequency change will now be described. Assume that a phase locked loop 100 is locked with N=3937. The output frequency is 944.88 MHz, the reference frequency 132 is 240 KHz, the current produced by the charge pumps is 2.5 mA and the VCO 110 has a gain or sensitivity of 50 MHz/V. Moreover, assume R=7.5 k.OMEGA., C.sub.1 =39 nF and C.sub.2 =1 nF.
When a new value of N is loaded, it is generally synchronous with the reference pulse. Thus, if N is changed to 4037, the charge pumps are active for about 105.8 nS after the next reference cycle, since the VCO is still running at 944.88 MHz for the previous cycle. See FIG. 5. This translates to a phase error of 0.160 radians and a duty cycle for the charge pumps of only 2.5%.
Ignoring transient behavior, the VCO control voltage will generally increase by (2.5 MA.105.8 nS)/40 nF=6.61 mV. This equates to a VCO frequency of 944.88+(0.00661 V.15 MHz/V)=944.98 MHz. Once again ignoring transients, the .function..sub.VCO /N pulse will lag the reference pulse by about (105.8+105.4 nS)-211.2 nS on the next comparison cycle. Charge pump duty cycle increases, but only to 5.1%. Accordingly, the charge pumps will be off most of the time until a significant phase error has developed. The resulting relationship between phase error and time averaged charge pump output is shown in FIG. 6.
The graph of FIG. 6 assumes that the primary charge pump 204 and the integral charge pump 402 of FIG. 4 are each actually formed of two charge pumps, a positive (P) type charge pump that pumps charge into (i.e. charges or sources) the associated capacitor, and a negative (N) type charge pump that pulls charge from (i.e. discharges or sinks) the associated capacitor. The relationship shown in FIG. 6 applies to phase errors which accumulate monotonically in either a positive or negative direction for a detector topology as shown in FIG. 7. The detector of FIG. 7 is well known to those having skill in the art and is implemented, for example, by a Philips Semiconductors integrated circuit SA7025, which is described in Philips Data Handbook IC17, Philips Semiconductors, 1996, at Page 744. A timing diagram for the circuit of FIG. 7 is shown in FIG. 8. By monotonicity, it is meant that without knowing the state of the phase/frequency detector, -.pi. is indistinguishable from +.pi.. Thus, whether the charge pump sources or sinks currents depends on whether or not the flip-flops in FIG. 7 have been reset previous to the occurrence of the .function..sub.VCO /N pulse. Since the state of the flip-flops depends on their history, absolute phase is not enough to predict their behavior.
Accordingly, conventional charge pumps are made large, so that they can source or sink large quantities of current, because their duty cycle is dependent on phase errors, and is thus well below 100% early on in the frequency adjustment. Thus, in order to transfer large amounts of charge to C.sub.1 in the short amount of time available, the charge pumps 204 and 402 generally must flow large currents. The need to source or sink large currents may increase the cost of the phase locked loop and/or may increase the die size of integrated circuit phase locked loops.